1. Field of the Invention
The invention relates to memories, and more particularly to memory output circuits.
2. Description of the Related Art
Referring to FIG. 1, a block diagram of at least a portion of a conventional memory circuit 100 is shown. The memory circuit 100 includes a memory cell array 120 and a memory output circuit 110. The memory cell array 120 includes a plurality of memory cells 121˜12n. The memory cells 121˜12n are read only memory (ROM) cells and are coupled between a bit line BL and a bit bar line BLB. Each of the memory cells 121˜12n includes two NMOS transistors and is coupled to a word line. For example, the memory cell 121 is coupled to a word line WL1 and includes two NMOS transistors 121a and 121b, and the memory cell 122 is coupled to a word line WL2 and includes two NMOS transistors 122a and 122b. The gates of both two NMOS transistors of the memory cells 121˜12n are coupled to the corresponding word lines, and the sources of both two NMOS transistors of the memory cells 121˜12n are coupled to a ground voltage GND.
Each of the memory cells 121˜12n stores a data bit which may have a bit value of “0” or “1”. Only one NMOS transistor of the memory cells 121˜12n has a drain coupled to the bit line BL or the bit bar line BLB. When a memory cell stores a bit value of “0”, a connection between a drain of a right NMOS transistor of the memory cell and the bit bar line BLB is burned down with a laser when the memory cell is programmed. For example, when the memory cell 122 stores a bit value of “0”, the drain of the NMOS transistor 122a is coupled to the bit line BL, and the drain of the NMOS transistor 122b is disconnected from the bit bar line BLB. When a memory cell stores a bit value of “1”, a connection between a drain of a left NMOS transistor of the memory cell and the bit line BL is burned down with a laser when the memory cell is programmed. For example, when the memory cell 121 stores a bit value of “1”, the drain of the NMOS transistor 121b is coupled to the bit bar line BLB, and the drain of the NMOS transistor 121a is disconnected from the bit line BL.
The conventional memory output circuit 110 includes a first pre-charge circuit 102, a second pre-charge circuit 106, and a Y-decoder circuit 104. Before data of the memory cell array 120 is output to the bit line BL and the bit bar line BLB, a first pre-charge signal PR triggers the first pre-charge circuit 102 to charge the bit line BL and the bit bar line BLB to a logic high voltage. Similarly, before data of the memory cell array 120 is output to the bit line BL and the bit bar line BLB, a second pre-charge signal PRB triggers the second pre-charge circuit 106 to charge a data line DL and a data bar line DLB to the logic high voltage.
A target memory cell selected from the memory cells 121˜12n of the memory cell array 120 is then read. The word line corresponding to the target memory cell is selected to turn on the NMOS transistors of the target memory cell. If the target memory cell stores a bit value of “0”, the left NMOS transistor couples the bit line BL to the ground voltage GND, lowering the voltage of the bit line BL to the ground voltage. If the target memory cell stores a bit value of “1”, the right NMOS transistor couples the bit bar line BLB to the ground voltage GND, lowering the voltage of the bit bar line BLB to the ground voltage. A selection signal Y1 is then enabled to turn on the NMOS transistors 116 and 118 of the Y-decoder circuit 104. When the selection signal Y1 is enabled, the NMOS transistors 116 and 118 respectively couple the bit line BL and the bit bar line BLB to the data line DL and the data bar line DLB. The data value of the target memory cell is therefore output to the data line DL and the data bar line DLB.
The conventional memory output circuit 110, however, has a disadvantage of a low operation speed. To isolate the bit line BL and the bit bar line BLB from the data line DL and the data bar line DLB, the NMOS transistors 116 and 118 of the Y-decoder circuit 104 have a high threshold voltage VTH. Because the NMOS transistors 116 and 118 have a high threshold voltage, the selection signal Y1 must be raised to a high level to turn on the NMOS transistors 116 and 118. Raising the voltage level of the selection signal Y1 requires a long time period of time, causing a delay in outputting of memory data and lowering the operation speed of the memory output circuit 100. To reduce the access time of a memory circuit, a memory output circuit with a high operation speed is therefore required.